This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-287498, filed Sep. 21, 2000; and No. 2000-354640, filed Nov. 21, 2000, the entire contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a power-on reset circuit which is used for, e.g., a semiconductor memory.
2. Description of the Related Art
A power-on reset circuit generates a power-on reset signal when an externally input power supply voltage reaches a predetermined value or more. A power-on reset signal is also used to initialize the state of a flip-flop circuit in a semiconductor chip or initialize an analog circuit such as a constant current generator or reference voltage generator.
In a semiconductor memory, for example, let VCC be the power supply voltage, Vlgc be the power supply voltage at which logic circuits such as flip-flops start operating, Valg be the power supply voltage at which analog circuits start operating, and VCCmin be the lower limit of the power supply voltage VCC determined from specifications. In this case, a power-on monitoring level Vpo which is the value of the power supply voltage VCC at which the power-on reset signal changes from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d must satisfy
max(Vlgc,Valg) less than Vpo less than VCCminxe2x80x83xe2x80x83(1)
where max(Vlgc,Valg) indicates a larger one of the power supply voltages Vlgc and Valg. Normally, the power supply voltage Valg is larger.
FIG. 1A shows the arrangement of a conventional power-on reset circuit. This power-on reset circuit has the following arrangement.
Two resistive elements R1 and R2 are connected in series between a VCC node to which an externally input power supply voltage VCC is supplied and a VSS node to which a ground potential VSS is supplied. The gate of a PMOS transistor QP is connected to a series-connection node A between the resistive elements R1 and R2. The source of the PMOS transistor QP is connected to the VCC node. A resistive element R3 is connected between the VSS node and the drain of the PMOS transistor QP.
The potential of a series-connection node B between the resistive element R3 and the drain of the PMOS transistor QP is input to two inverters 291 and 292 which use the power supply voltage VCC as the operation power supply. The output from the latter inverter 292 is used as a power-on reset signal POR.
The operation of the power-on reset circuit with the above arrangement will be described. The threshold value of the PMOS transistor QP is represented by Vtp. Immediately after the power supply voltage VCC is supplied, the PMOS transistor QP is kept OFF, the potential of the node B is kept at xe2x80x9cLxe2x80x9d, and the output potential of the latter inverter 292 is kept at xe2x80x9cLxe2x80x9d.
As shown in FIG. 1B, when the power supply voltage VCC rises and exceeds the power-on monitoring level Vpo=(R1+R2)|Vtp|/R1 at time t1, the PMOS transistor QP in FIG. 1A is turned on. As the potential of the node B changes to xe2x80x9cHxe2x80x9d, and the power-on reset signal POR changes to xe2x80x9cHxe2x80x9d, the power-on reset signal POR is generated. The resistance value ratio between the resistive elements R1 and R2 is determined such that relation (1) is satisfied.
In the conventional power-on reset circuit as described above, the power-on monitoring level Vpo depends on the threshold value Vtp of the PMOS transistor QP. The threshold value Vtp of the PMOS transistor QP has a variation based on the manufacturing process and also changes depending on the temperature. For this reason, the power-on monitoring level Vpo also largely changes due to the variation in threshold value Vtp of the PMOS transistor QP or the temperature, and the condition (1) is not satisfied. A range indicated by arrows in FIG. 1B shows the variation in power-on monitoring level Vpo due to the variation in threshold value Vtp of the PMOS transistor QP or the temperature. FIG. 1B shows a state wherein the relation (1) is satisfied.
In a semiconductor memory having a capacity as large as 1 Gbit, to realize low VCC operation by employing a ROM fuse as a fuse element, various power supply voltages and the read-out operation of the ROM fuse at the power-on time must be taken into consideration. For example, if 2.3-V operation on the specifications and 2.1-V operation on the design are to be guaranteed, -1.6-V operation must be guaranteed in the power-on reset circuit. However, use of such a low power supply voltage is basically impossible because a Wilson circuit or differential amplifier as a current source circuit does not operate.
As described above, in the conventional power-on reset circuit, the power-on monitoring level Vpo depends on the threshold value Vtp of the PMOS transistor QP, and the threshold value Vtp has a variation based on the manufacturing process and also changes depending on the temperature. For this reason, the power-on monitoring level Vpo also largely changes due to the variation in threshold value Vtp of the PMOS transistor QP or the temperature, and the normal operation condition is not satisfied.
Hence, implementation of a semiconductor device having a power-on reset circuit whose power-on monitoring level changes little due to a variation in threshold value of an element used or the temperature is required.
In addition, implementation of a semiconductor device which can operate a Wilson circuit or reference voltage generator as a current source circuit even when a low power supply voltage is used is desired.
Furthermore, implementation of a semiconductor memory device capable of stable read-out operation even when the power supply voltage is dropped in normal read-out operation is desired.
According to the first aspect of the present invention, there is provided a semiconductor device comprising:
an oscillator which starts generating a clock pulse when an externally supplied power supply voltage becomes higher than a first voltage;
a charge pump circuit configured to execute charge pumping operation upon receiving the clock pulse; and
a voltage monitor configured to generate a power-on reset signal upon receiving an output voltage from the charge pump circuit.
According to the second aspect of the present invention, there is provided a semiconductor memory device comprising:
a memory cell array in which a plurality of memory cells are arranged;
a register configured to store data read out from the plurality of memory cells;
a reference voltage circuit configured to generate a reference voltage; and
a charge pump circuit configured to charge-pump a power supply voltage for the reference voltage circuit during a period of a read-out operation when the data are read out from the plurality of memory cells.